1. Field of the Invention
The invention relates to a semiconductor device and a method of fabricating the same, and more particularly to an improvement in formation of a gate electrode of a semiconductor device.
2. Description of the Related Art
A currently available semiconductor device including a MOS transistor has oxides for isolating device formation regions from one another, formed by thermally oxidizing selected regions, and a polycide gate electrode having a two-layers structure including a polysilicon film and a silicide film, made of, for example, tungsten silicide, deposited on the polysilicon film.
Among such semiconductor devices, a 256 Mb DRAM having a micro-ordered structure and high integration includes device isolation regions having a width of 0.25 .mu.m, device formation regions having a width of 0.25 .mu.m, oxide films for device isolation having a thickness of 0.3 .mu.m, and a gate electrode having a width of 0.25 .mu.m. In order to form such micrometer-sized patterns, there is used lithography technique in which a short wavelength light such as KrF excimer laser is used as a light source.
FIGS. 1A and 1B illustrate a conventional method of fabricating a resist mask to be used for formation of a gate electrode. As illustrated in FIG. 1A, there are formed a plurality of oxides 3 on a surface of a substrate 1 for isolating device formation regions from one another. A gate polysilicon film 5 is formed over the substrate 1, and a gate silicide film 6 is formed over the gate polysilicon film 5. The gate silicide film 6 is covered with photoresist 7. Both the gate polysilicon film 5 and gate silicide 6 have irregularities on surfaces thereof which reflect raises of the oxides 3.
When a resist mask to be used for formation of a gate electrode is to be formed on the gate silicide film 6, incident lights L reflected by corners of raised portions of the gate silicide film 6 are directed to a light-impermeable mask 18. As a result, after the photoresist 7 is etched for removal, a residual resist 7-1 has a portion 7-2 narrower than a width of the mask 18 above a device formation region, as illustrated in FIG. 1B.
An attempt to solve the above mentioned problem has been proposed in U.S. Pat. No. 5,346,587 issued on Sep. 13, 1994 to Doan et al. FIGS. 2A to 2D are cross-sectional views showing respective step of a method proposed by Doan et al.
As illustrated in FIG. 2A, there are formed oxide films 3 for isolation of device formation regions and gate oxide films 2 on a substrate 1 in a conventional way. Then, a thick gate polysilicon film 5 is formed on the substrate 1 usually by low pressure chemical vapor deposition (LPCVD). Since polysilicon has superior coverage characteristic, the gate polysilicon film 5 has a top surface reflecting a shape of raised portions of the oxide films 3.
Then, as illustrated in FIG. 2B, the gate polysilicon film 5 is planarized. A gate silicide film 6 made of tungsten silicide is formed on the planarized gate polysilicon film 5-1. The gate silicide film 6 has a flat top surface which reflects a flat surface of the underlying polysilicon film 5-1. Then, photoresist is deposited over the gate silicide film 6, and thereafter the photoresist is patterned into photoresist 7-2 by means of KrF excimer laser beam to form a pattern of a gate electrode 8.
The KrF excimer laser beam reflects at a surface of the gate silicide film 6. However, since the gate silicide film 6 has a flat surface, there does not occur irregular reflection unlike the conventional method as illustrated in FIG. 1A. Accordingly, the patterned photoresist 7-2 can have exactly the same shape as a mask.
Then, both the gate silicide film 6 and the gate polysilicon film 5-1 are etched by using the photoresist 7-2 as a mask in a conventional way to thereby form the gate electrode 8, as illustrated in FIG. 2C.
The above mentioned method of U.S. Pat. No. 5,346,587 has a problem as follows. In this method, when the gate polysilicon film 5 is to be planarized, the amount that the gate polysilicon film 5 is to be etched is empirically time-controlled. However, it is very difficult or almost impossible to observe a thickness of the gate polysilicon film 5 while the polysilicon film 5 is being etched. Thus, there is always a risk of over-etching of the gate polysilicon film 5. If the gate polysilicon film 5 is over-etched, as illustrated in FIG. 2D, the gate oxide films 2 and/or the substrate 1 may be exposed.
If the gate silicide film 6 makes direct contact with an exposed surface of the gate oxide films 2, a threshold voltage of a transistor is forced to vary due to a difference in work function between the gate silicide film 6 and the substrate 1.
In addition, in the process of formation of a gate electrode, if the gate polysilicon film 5 is thin, the gate oxide film 2 may be etched while the gate silicide film 6 lying on the thin gate polysilicon film 5 is being etched. If the gate oxide film 2 is etched, even the substrate 1 might be etched.
Thus, those skilled in the art could adopt a method of forming a mark for detecting an end point of etching in order to prevent over-etching of the gate polysilicon film 5. However, forming such a mark in additional steps would unpreferably increase the number of fabrication steps.